/*
 * @[H]:  Copyright (c) 2021 Phytium Information Technology, Inc. 
 * 
 *  SPDX-License-Identifier: Apache-2.0. 
 * 
 * @Date: 2021-07-19 14:46:07
 * @LastEditTime: 2021-07-23 17:08:39
 * @Description:  Description of file
 * @Modify History: 
 * * * Ver   Who        Date         Changes
 * * ----- ------     --------    --------------------------------------
 */

#ifndef BSP_DRIVERS_ETH_FMAC_HW_H
#define BSP_DRIVERS_ETH_FMAC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "parameters.h"
#include "ft_io.h"
#include "ft_types.h"

#define FXMAC_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in \
                                       bytes, 64, 128, ... 10240 */
#define FXMAC_RX_BUF_SIZE_JUMBO 10240U

#define FXMAC_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a \
                                     unit, this is HW setup */

#define FXMAC_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define FXMAC_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */

#define FXMAC_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */

    /************************** Constant Definitions *****************************/

#define FXMAC_MAX_MAC_ADDR 4U /**< Maxmum number of mac address \
                                     supported */
#define FXMAC_MAX_TYPE_ID 4U  /**< Maxmum number of type id supported */

#ifdef __aarch64__
#define FXMAC_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment \
                                     on the local bus */
#else

#define FXMAC_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment \
                                     on the local bus */
#endif
#define FXMAC_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using  \
                                         options that impose alignment      \
                                         restrictions on the buffer data on \
                                         the local bus */

#define FXMAC_NWCTRL_OFFSET 0x00000000U  /**< Network Control reg */
#define FXMAC_NWCFG_OFFSET 0x00000004U   /**< Network Config reg */
#define FXMAC_NWSR_OFFSET 0x00000008U    /**< Network Status reg */
#define FXMAC_GEM_USRIO 0x000000cU       /* User IO */
#define FXMAC_DMACR_OFFSET 0x00000010U   /**< DMA Control reg */
#define FXMAC_TXSR_OFFSET 0x00000014U    /**< TX Status reg */
#define FXMAC_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define FXMAC_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define FXMAC_RXSR_OFFSET 0x00000020U    /**< RX Status reg */

#define FXMAC_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define FXMAC_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define FXMAC_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define FXMAC_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */

#define FXMAC_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define FXMAC_RXPAUSE_OFFSET 0x00000038U  /**< RX Pause Time reg */
#define FXMAC_TXPAUSE_OFFSET 0x0000003CU  /**< TX Pause Time reg */

#define FXMAC_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define FXMAC_GEM_HSMAC 0x0050               /* Hs mac config register*/
#define FXMAC_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */

#define FXMAC_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define FXMAC_HASHH_OFFSET 0x00000084U /**< Hash High address reg */

#define FXMAC_GEM_SA1B 0x0088 /* Specific1 Bottom */
#define FXMAC_GEM_SA1T 0x008C /* Specific1 Top */
#define FXMAC_GEM_SA2B 0x0090 /* Specific2 Bottom */
#define FXMAC_GEM_SA2T 0x0094 /* Specific2 Top */
#define FXMAC_GEM_SA3B 0x0098 /* Specific3 Bottom */
#define FXMAC_GEM_SA3T 0x009C /* Specific3 Top */
#define FXMAC_GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define FXMAC_GEM_SA4T 0x00A4 /* Specific4 Top */

#define FXMAC_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define FXMAC_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define FXMAC_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define FXMAC_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */

#define FXMAC_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */

#define FXMAC_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low \
                                               reg */
#define FXMAC_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High \
                                               reg */

#define FXMAC_TXCNT_OFFSET 0x00000108U      /**< Error-free Frmaes \
                                                   transmitted counter */
#define FXMAC_TXBCCNT_OFFSET 0x0000010CU    /**< Error-free Broadcast \
                                                   Frames counter*/
#define FXMAC_TXMCCNT_OFFSET 0x00000110U    /**< Error-free Multicast \
                                                   Frame counter */
#define FXMAC_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted \
                                                   Counter */
#define FXMAC_TX64CNT_OFFSET 0x00000118U    /**< Error-free 64 byte Frames \
                                                   Transmitted counter */
#define FXMAC_TX65CNT_OFFSET 0x0000011CU    /**< Error-free 65-127 byte \
                                                   Frames Transmitted   \
                                                   counter */
#define FXMAC_TX128CNT_OFFSET 0x00000120U   /**< Error-free 128-255 byte \
                                                   Frames Transmitted    \
                                                   counter*/
#define FXMAC_TX256CNT_OFFSET 0x00000124U   /**< Error-free 256-511 byte \
                                                   Frames transmitted    \
                                                   counter */
#define FXMAC_TX512CNT_OFFSET 0x00000128U   /**< Error-free 512-1023 byte \
                                                   Frames transmitted     \
                                                   counter */
#define FXMAC_TX1024CNT_OFFSET 0x0000012CU  /**< Error-free 1024-1518 byte \
                                                   Frames transmitted      \
                                                   counter */
#define FXMAC_TX1519CNT_OFFSET 0x00000130U  /**< Error-free larger than \
                                                   1519 byte Frames     \
                                                   transmitted counter */
#define FXMAC_TXURUNCNT_OFFSET 0x00000134U  /**< TX under run error \
                                                   counter */

#define FXMAC_SNGLCOLLCNT_OFFSET 0x00000138U   /**< Single Collision Frame \
                                                      Counter */
#define FXMAC_MULTICOLLCNT_OFFSET 0x0000013CU  /**< Multiple Collision Frame \
                                                      Counter */
#define FXMAC_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame \
                                                      Counter */
#define FXMAC_LATECOLLCNT_OFFSET 0x00000144U   /**< Late Collision Frame \
                                                      Counter */
#define FXMAC_TXDEFERCNT_OFFSET 0x00000148U    /**< Deferred Transmission \
                                                      Frame Counter */
#define FXMAC_TXCSENSECNT_OFFSET 0x0000014CU   /**< Transmit Carrier Sense \
                                                      Error Counter */

#define FXMAC_OCTRXL_OFFSET 0x00000150U /**< Octects Received register \
                                               Low */
#define FXMAC_OCTRXH_OFFSET 0x00000154U /**< Octects Received register \
                                               High */

#define FXMAC_RXCNT_OFFSET 0x00000158U       /**< Error-free Frames \
                                                    Received Counter */
#define FXMAC_RXBROADCNT_OFFSET 0x0000015CU  /**< Error-free Broadcast \
                                                    Frames Received Counter */
#define FXMAC_RXMULTICNT_OFFSET 0x00000160U  /**< Error-free Multicast \
                                                    Frames Received Counter */
#define FXMAC_RXPAUSECNT_OFFSET 0x00000164U  /**< Pause Frames \
                                                    Received Counter */
#define FXMAC_RX64CNT_OFFSET 0x00000168U     /**< Error-free 64 byte Frames \
                                                    Received Counter */
#define FXMAC_RX65CNT_OFFSET 0x0000016CU     /**< Error-free 65-127 byte \
                                                    Frames Received Counter */
#define FXMAC_RX128CNT_OFFSET 0x00000170U    /**< Error-free 128-255 byte \
                                                    Frames Received Counter */
#define FXMAC_RX256CNT_OFFSET 0x00000174U    /**< Error-free 256-512 byte \
                                                    Frames Received Counter */
#define FXMAC_RX512CNT_OFFSET 0x00000178U    /**< Error-free 512-1023 byte \
                                                    Frames Received Counter */
#define FXMAC_RX1024CNT_OFFSET 0x0000017CU   /**< Error-free 1024-1518 byte \
                                                    Frames Received Counter */
#define FXMAC_RX1519CNT_OFFSET 0x00000180U   /**< Error-free 1519-max byte \
                                                    Frames Received Counter */
#define FXMAC_RXUNDRCNT_OFFSET 0x00000184U   /**< Undersize Frames Received \
                                                    Counter */
#define FXMAC_RXOVRCNT_OFFSET 0x00000188U    /**< Oversize Frames Received \
                                                    Counter */
#define FXMAC_RXJABCNT_OFFSET 0x0000018CU    /**< Jabbers Received \
                                                    Counter */
#define FXMAC_RXFCSCNT_OFFSET 0x00000190U    /**< Frame Check Sequence \
                                                    Error Counter */
#define FXMAC_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error \
                                                    Counter */
#define FXMAC_RXSYMBCNT_OFFSET 0x00000198U   /**< Symbol Error Counter */
#define FXMAC_RXALIGNCNT_OFFSET 0x0000019CU  /**< Alignment Error Counter */
#define FXMAC_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error \
                                                    Counter */
#define FXMAC_RXORCNT_OFFSET 0x000001A4U     /**< Receive Overrun Counter */
#define FXMAC_RXIPCCNT_OFFSET 0x000001A8U    /**< IP header Checksum Error \
                                                    Counter */
#define FXMAC_RXTCPCCNT_OFFSET 0x000001ACU   /**< TCP Checksum Error \
                                                    Counter */
#define FXMAC_RXUDPCCNT_OFFSET 0x000001B0U   /**< UDP Checksum Error \
                                                    Counter */
#define FXMAC_LAST_OFFSET 0x000001B4U        /**< Last statistic counter \
                            offset, for clearing */

#define FXMAC_1588_SEC_OFFSET 0x000001D0U       /**< 1588 second counter */
#define FXMAC_1588_NANOSEC_OFFSET 0x000001D4U   /**< 1588 nanosecond counter */
#define FXMAC_1588_ADJ_OFFSET 0x000001D8U       /**< 1588 nanosecond \
                               adjustment counter */
#define FXMAC_1588_INC_OFFSET 0x000001DCU       /**< 1588 nanosecond \
                               increment counter */
#define FXMAC_PTP_TXSEC_OFFSET 0x000001E0U      /**< 1588 PTP transmit second \
                               counter */
#define FXMAC_PTP_TXNANOSEC_OFFSET 0x000001E4U  /**< 1588 PTP transmit \
                               nanosecond counter */
#define FXMAC_PTP_RXSEC_OFFSET 0x000001E8U      /**< 1588 PTP receive second \
                               counter */
#define FXMAC_PTP_RXNANOSEC_OFFSET 0x000001ECU  /**< 1588 PTP receive \
                               nanosecond counter */
#define FXMAC_PTPP_TXSEC_OFFSET 0x000001F0U     /**< 1588 PTP peer transmit \
                               second counter */
#define FXMAC_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit \
                              nanosecond counter */
#define FXMAC_PTPP_RXSEC_OFFSET 0x000001F8U     /**< 1588 PTP peer receive \
                               second counter */
#define FXMAC_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive \
                              nanosecond counter */

#define FXMAC_INTQ1_STS_OFFSET 0x00000400U      /**< Interrupt Q1 Status \
                             reg */
#define FXMAC_TXQ1BASE_OFFSET 0x00000440U       /**< TX Q1 Base address \
                             reg */
#define FXMAC_RXQ1BASE_OFFSET 0x00000480U       /**< RX Q1 Base address \
                             reg */
#define FXMAC_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base \
                           reg */
#define FXMAC_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base \
                           reg */
#define FXMAC_INTQ1_IER_OFFSET 0x00000600U      /**< Interrupt Q1 Enable \
                             reg */
#define FXMAC_INTQ1_IDR_OFFSET 0x00000620U      /**< Interrupt Q1 Disable \
                             reg */
#define FXMAC_INTQ1_IMR_OFFSET 0x00000640U      /**< Interrupt Q1 Mask \
                             reg */

#define FXMAC_GEM_SRC_SEL_LN 0x1C04
#define FXMAC_GEM_DIV_SEL0_LN 0x1C08
#define FXMAC_GEM_DIV_SEL1_LN 0x1C0C
#define FXMAC_GEM_PMA_XCVR_POWER_STATE 0x1C10
#define FXMAC_GEM_SPEED_MODE 0x1C14
#define FXMAC_GEM_MII_SELECT 0x1C18
#define FXMAC_GEM_SEL_MII_ON_RGMII 0x1C1C
#define FXMAC_GEM_TX_CLK_SEL0 0x1C20
#define FXMAC_GEM_TX_CLK_SEL1 0x1C24
#define FXMAC_GEM_TX_CLK_SEL2 0x1C28
#define FXMAC_GEM_TX_CLK_SEL3 0x1C2C
#define FXMAC_GEM_RX_CLK_SEL0 0x1C30
#define FXMAC_GEM_RX_CLK_SEL1 0x1C34
#define FXMAC_GEM_CLK_250M_DIV10_DIV100_SEL 0x1C38
#define FXMAC_GEM_TX_CLK_SEL5 0x1C3C
#define FXMAC_GEM_TX_CLK_SEL6 0x1C40
#define FXMAC_GEM_RX_CLK_SEL4 0x1C44
#define FXMAC_GEM_RX_CLK_SEL5 0x1C48
#define FXMAC_GEM_TX_CLK_SEL3_0 0x1C70
#define FXMAC_GEM_TX_CLK_SEL4_0 0x1C74
#define FXMAC_GEM_RX_CLK_SEL3_0 0x1C78
#define FXMAC_GEM_RX_CLK_SEL4_0 0x1C7C
#define FXMAC_GEM_RGMII_TX_CLK_SEL0 0x1C80
#define FXMAC_GEM_RGMII_TX_CLK_SEL1 0x1C84

/**
 * @name interrupts bit definitions
 * Bits definitions are same in FXMAC_ISR_OFFSET,
 * FXMAC_IER_OFFSET, FXMAC_IDR_OFFSET, and FXMAC_IMR_OFFSET
 * @{
 */
#define FXMAC_IXR_PTPPSTX_MASK 0x02000000U  /**< PTP Pdelay_resp TXed */
#define FXMAC_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
#define FXMAC_IXR_PTPPSRX_MASK 0x00800000U  /**< PTP Pdelay_resp RXed */
#define FXMAC_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */

#define FXMAC_IXR_PTPSTX_MASK 0x00200000U  /**< PTP Sync TXed */
#define FXMAC_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
#define FXMAC_IXR_PTPSRX_MASK 0x00080000U  /**< PTP Sync RXed */
#define FXMAC_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */

#define FXMAC_IXR_PAUSETX_MASK 0x00004000U    /**< Pause frame transmitted */
#define FXMAC_IXR_PAUSEZERO_MASK 0x00002000U  /**< Pause time has reached \
                                                     zero */
#define FXMAC_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define FXMAC_IXR_HRESPNOK_MASK 0x00000800U   /**< hresp not ok */
#define FXMAC_IXR_RXOVR_MASK 0x00000400U      /**< Receive overrun occurred */
#define FXMAC_IXR_TXCOMPL_MASK 0x00000080U    /**< Frame transmitted ok */
#define FXMAC_IXR_TXEXH_MASK 0x00000040U      /**< Transmit err occurred or \
                                                     no buffers*/
#define FXMAC_IXR_RETRY_MASK 0x00000020U      /**< Retry limit exceeded */
#define FXMAC_IXR_URUN_MASK 0x00000010U       /**< Transmit underrun */
#define FXMAC_IXR_TXUSED_MASK 0x00000008U     /**< Tx buffer used bit read */
#define FXMAC_IXR_RXUSED_MASK 0x00000004U     /**< Rx buffer used bit read */
#define FXMAC_IXR_FRAMERX_MASK 0x00000002U    /**< Frame received ok */
#define FXMAC_IXR_MGMNT_MASK 0x00000001U      /**< PHY management complete */
#define FXMAC_IXR_ALL_MASK 0x00007FFFU        /**< Everything! */

/** @name network control register bit definitions
 * @{
 */
#define FXMAC_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from \
                            Rx SRAM */
#define FXMAC_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum \
                                                         pause frame */
#define FXMAC_NWCTRL_PAUSETX_MASK 0x00000800U     /**< Transmit pause frame */
#define FXMAC_NWCTRL_HALTTX_MASK 0x00000400U      /**< Halt transmission \
                                                         after current frame */
#define FXMAC_NWCTRL_STARTTX_MASK 0x00000200U     /**< Start tx (tx_go) */

#define FXMAC_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to \
                                                     stat counters */
#define FXMAC_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic \
                                                     registers */
#define FXMAC_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic \
                                                     registers */
#define FXMAC_NWCTRL_MDEN_MASK 0x00000010U    /**< Enable MDIO port */
#define FXMAC_NWCTRL_TXEN_MASK 0x00000008U    /**< Enable transmit */
#define FXMAC_NWCTRL_RXEN_MASK 0x00000004U    /**< Enable receive */
#define FXMAC_NWCTRL_LOOPEN_MASK 0x00000002U  /**< local loopback */
    /*@}*/

/**< External address match enable */
#define FXMAC_NWCFG_PCSSEL_MASK 0x00000800U      /**< PCS Select */
#define FXMAC_NWCFG_1000_MASK 0x00000400U        /**< 1000 Mbps */
#define FXMAC_NWCFG_1536RXEN_MASK 0x00000100U    /**< Enable 1536 byte \
                                                        frames reception */
#define FXMAC_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash \
                                                        frames */
#define FXMAC_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash \
                                                        frames */
#define FXMAC_NWCFG_BCASTDI_MASK 0x00000020U     /**< Do not receive \
                                                        broadcast frames */
#define FXMAC_NWCFG_COPYALLEN_MASK 0x00000010U   /**< Copy all frames */
#define FXMAC_NWCFG_JUMBO_MASK 0x00000008U       /**< Jumbo frames */
#define FXMAC_NWCFG_NVLANDISC_MASK 0x00000004U   /**< Receive only VLAN \
                                                        frames */
#define FXMAC_NWCFG_FDEN_MASK 0x00000002U        /**< full duplex */
#define FXMAC_NWCFG_100_MASK 0x00000001U         /**< 100 Mbps */
#define FXMAC_NWCFG_RESET_MASK 0x00080000U       /**< reset value */
    /*@}*/

/* Receive buffer descriptor status words bit positions.
 * Receive buffer descriptor consists of two 32-bit registers,
 * the first - word0 contains a 32-bit word aligned address pointing to the
 * address of the buffer. The lower two bits make up the wrap bit indicating
 * the last descriptor and the ownership bit to indicate it has been used by
 * the XEmacPs.
 * The following register - word1, contains status information regarding why
 * the frame was received (the filter match condition) as well as other
 * useful info.
 * @{
 */
#define FXMAC_RXBUF_BCAST_MASK 0x80000000U     /**< Broadcast frame */
#define FXMAC_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define FXMAC_RXBUF_UNIHASH_MASK 0x20000000U   /**< Unicast hashed frame */
#define FXMAC_RXBUF_EXH_MASK 0x08000000U       /**< buffer exhausted */
#define FXMAC_RXBUF_AMATCH_MASK 0x06000000U    /**< Specific address \
                                                      matched */
#define FXMAC_RXBUF_IDFOUND_MASK 0x01000000U   /**< Type ID matched */
#define FXMAC_RXBUF_IDMATCH_MASK 0x00C00000U   /**< ID matched mask */
#define FXMAC_RXBUF_VLAN_MASK 0x00200000U      /**< VLAN tagged */
#define FXMAC_RXBUF_PRI_MASK 0x00100000U       /**< Priority tagged */
#define FXMAC_RXBUF_VPRI_MASK 0x000E0000U      /**< Vlan priority */
#define FXMAC_RXBUF_CFI_MASK 0x00010000U       /**< CFI frame */
#define FXMAC_RXBUF_EOF_MASK 0x00008000U       /**< End of frame. */
#define FXMAC_RXBUF_SOF_MASK 0x00004000U       /**< Start of frame. */
#define FXMAC_RXBUF_LEN_MASK 0x00001FFFU       /**< Mask for length field */
#define FXMAC_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */

#define FXMAC_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define FXMAC_RXBUF_NEW_MASK 0x00000001U  /**< Used bit.. */
#define FXMAC_RXBUF_ADD_MASK 0xFFFFFFFCU  /**< Mask for address */
/*
 * @}
 */

/* Transmit buffer descriptor status words bit positions.
 * Transmit buffer descriptor consists of two 32-bit registers,
 * the first - word0 contains a 32-bit address pointing to the location of
 * the transmit data.
 * The following register - word1, consists of various information to control
 * the XEmacPs transmit process.  After transmit, this is updated with status
 * information, whether the frame was transmitted OK or why it had failed.
 * @{
 */
#define FXMAC_TXBUF_USED_MASK 0x80000000U  /**< Used bit. */
#define FXMAC_TXBUF_WRAP_MASK 0x40000000U  /**< Wrap bit, last descriptor */
#define FXMAC_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define FXMAC_TXBUF_URUN_MASK 0x10000000U  /**< Transmit underrun occurred */
#define FXMAC_TXBUF_EXH_MASK 0x08000000U   /**< Buffers exhausted */
#define FXMAC_TXBUF_TCP_MASK 0x04000000U   /**< Late collision. */
#define FXMAC_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define FXMAC_TXBUF_LAST_MASK 0x00008000U  /**< Last buffer */
#define FXMAC_TXBUF_LEN_MASK 0x00003FFFU   /**< Mask for length field */
/*
 * @}
 */

/** @name network configuration register bit definitions
 * @{
 */
#define FXMAC_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of \
                                                        non-standard preamble */
#define FXMAC_NWCFG_IPDSTRETCH_MASK 0x10000000U  /**< enable transmit IPG */
#define FXMAC_NWCFG_SGMIIEN_MASK 0x08000000U     /**< SGMII Enable */
#define FXMAC_NWCFG_FCSIGNORE_MASK 0x04000000U   /**< disable rejection of \
                                                        FCS error */
#define FXMAC_NWCFG_HDRXEN_MASK 0x02000000U      /**< RX half duplex */
#define FXMAC_NWCFG_RXCHKSUMEN_MASK 0x01000000U  /**< enable RX checksum \
                                                        offload */
#define FXMAC_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause \
                                                        Frames to memory */
#define FXMAC_NWCFG_DWIDTH_64_MASK 0x00200000U   /**< 64 bit Data bus width */
#define FXMAC_NWCFG_MDC_SHIFT_MASK 18U           /**< shift bits for MDC */
#define FXMAC_NWCFG_MDCCLKDIV_MASK 0x001C0000U   /**< MDC Mask PCLK divisor */
#define FXMAC_NWCFG_FCSREM_MASK 0x00020000U      /**< Discard FCS from \
                                                        received frames */
#define FXMAC_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define FXMAC_NWCFG_RXOFFS_MASK 0x0000C000U      /**< RX buffer offset */
#define FXMAC_NWCFG_PAUSEEN_MASK 0x00002000U     /**< Enable pause RX */
#define FXMAC_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define FXMAC_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define FXMAC_NWCFG_PCSSEL_MASK 0x00000800U      /**< PCS Select */
#define FXMAC_NWCFG_1000_MASK 0x00000400U        /**< 1000 Mbps */
#define FXMAC_NWCFG_1536RXEN_MASK 0x00000100U    /**< Enable 1536 byte \
                                                        frames reception */
#define FXMAC_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash \
                                                        frames */
#define FXMAC_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash \
                                                        frames */
#define FXMAC_NWCFG_BCASTDI_MASK 0x00000020U     /**< Do not receive \
                                                        broadcast frames */
#define FXMAC_NWCFG_COPYALLEN_MASK 0x00000010U   /**< Copy all frames */
#define FXMAC_NWCFG_JUMBO_MASK 0x00000008U       /**< Jumbo frames */
#define FXMAC_NWCFG_NVLANDISC_MASK 0x00000004U   /**< Receive only VLAN \
                                                        frames */
#define FXMAC_NWCFG_FDEN_MASK 0x00000002U        /**< full duplex */
#define FXMAC_NWCFG_100_MASK 0x00000001U         /**< 100 Mbps */
#define FXMAC_NWCFG_RESET_MASK 0x00080000U       /**< reset value */
/*@}*/

/**
 * @name receive status register bit definitions
 * @{
 */
#define FXMAC_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define FXMAC_RXSR_RXOVR_MASK 0x00000004U    /**< Receive overrun */
#define FXMAC_RXSR_FRAMERX_MASK 0x00000002U  /**< Frame received OK */
#define FXMAC_RXSR_BUFFNA_MASK 0x00000001U   /**< RX buffer used bit set */

#define FXMAC_RXSR_ERROR_MASK ((u32)FXMAC_RXSR_HRESPNOK_MASK | \
                               (u32)FXMAC_RXSR_RXOVR_MASK |    \
                               (u32)FXMAC_RXSR_BUFFNA_MASK)

#define FXMAC_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */

/** @name DMA control register bit definitions
 * @{
 */
#define FXMAC_DMACR_ADDR_WIDTH_64 0x40000000U        /**< 64 bit address bus */
#define FXMAC_DMACR_TXEXTEND_MASK 0x20000000U        /**< Tx Extended desc mode */
#define FXMAC_DMACR_RXEXTEND_MASK 0x10000000U        /**< Rx Extended desc mode */
#define FXMAC_DMACR_RXBUF_MASK 0x00FF0000U           /**< Mask bit for RX buffer \
                                                       size */
#define FXMAC_DMACR_RXBUF_SHIFT 16U                  /**< Shift bit for RX buffer \
                                                           size */
#define FXMAC_DMACR_TCPCKSUM_MASK 0x00000800U        /**< enable/disable TX \
                                                           checksum offload */
#define FXMAC_DMACR_TXSIZE_MASK 0x00000400U          /**< TX buffer memory size */
#define FXMAC_DMACR_RXSIZE_MASK 0x00000300U          /**< RX buffer memory size */
#define FXMAC_DMACR_ENDIAN_MASK 0x00000080U          /**< endian configuration */
#define FXMAC_DMACR_BLENGTH_MASK 0x0000001FU         /**< buffer burst length */
#define FXMAC_DMACR_SINGLE_AHB_AXI_BURST 0x00000001U /**< single AHB_AXI bursts */
#define FXMAC_DMACR_INCR4_AHB_AXI_BURST 0x00000004U  /**< 4 bytes AHB_AXI bursts */
#define FXMAC_DMACR_INCR8_AHB_AXI_BURST 0x00000008U  /**< 8 bytes AHB_AXI bursts */
#define FXMAC_DMACR_INCR16_AHB_AXI_BURST 0x00000010U /**< 16 bytes AHB_AXI bursts */
/*@}*/

/**
 * @name interrupts bit definitions
 * Bits definitions are same in FXMAC_ISR_OFFSET,
 * FXMAC_IER_OFFSET, FXMAC_IDR_OFFSET, and FXMAC_IMR_OFFSET
 * @{
 */
#define FXMAC_IXR_PTPPSTX_MASK 0x02000000U  /**< PTP Pdelay_resp TXed */
#define FXMAC_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
#define FXMAC_IXR_PTPPSRX_MASK 0x00800000U  /**< PTP Pdelay_resp RXed */
#define FXMAC_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */

#define FXMAC_IXR_PTPSTX_MASK 0x00200000U  /**< PTP Sync TXed */
#define FXMAC_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
#define FXMAC_IXR_PTPSRX_MASK 0x00080000U  /**< PTP Sync RXed */
#define FXMAC_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */

#define FXMAC_IXR_PAUSETX_MASK 0x00004000U    /**< Pause frame transmitted */
#define FXMAC_IXR_PAUSEZERO_MASK 0x00002000U  /**< Pause time has reached \
                                                     zero */
#define FXMAC_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define FXMAC_IXR_HRESPNOK_MASK 0x00000800U   /**< hresp not ok */
#define FXMAC_IXR_RXOVR_MASK 0x00000400U      /**< Receive overrun occurred */
#define FXMAC_IXR_TXCOMPL_MASK 0x00000080U    /**< Frame transmitted ok */
#define FXMAC_IXR_TXEXH_MASK 0x00000040U      /**< Transmit err occurred or \
                                                     no buffers*/
#define FXMAC_IXR_RETRY_MASK 0x00000020U      /**< Retry limit exceeded */
#define FXMAC_IXR_URUN_MASK 0x00000010U       /**< Transmit underrun */
#define FXMAC_IXR_TXUSED_MASK 0x00000008U     /**< Tx buffer used bit read */
#define FXMAC_IXR_RXUSED_MASK 0x00000004U     /**< Rx buffer used bit read */
#define FXMAC_IXR_FRAMERX_MASK 0x00000002U    /**< Frame received ok */
#define FXMAC_IXR_MGMNT_MASK 0x00000001U      /**< PHY management complete */
#define FXMAC_IXR_ALL_MASK 0x00007FFFU        /**< Everything! */

#define FXMAC_IXR_TX_ERR_MASK ((u32)FXMAC_IXR_TXEXH_MASK | \
                               (u32)FXMAC_IXR_RETRY_MASK | \
                               (u32)FXMAC_IXR_URUN_MASK)

#define FXMAC_IXR_RX_ERR_MASK ((u32)FXMAC_IXR_HRESPNOK_MASK | \
                               (u32)FXMAC_IXR_RXUSED_MASK |   \
                               (u32)FXMAC_IXR_RXOVR_MASK)

/*@}*/

/** @name network status register bit definitaions
 * @{
 */
#define FXMAC_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define FXMAC_NWSR_MDIO_MASK 0x00000002U     /**< Status of mdio_in */
/*@}*/

/** @name PHY Maintenance bit definitions
 * @{
 */
#define FXMAC_PHYMNTNC_OP_MASK 0x40020000U   /**< operation mask bits */
#define FXMAC_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define FXMAC_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define FXMAC_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define FXMAC_PHYMNTNC_REG_MASK 0x007C0000U  /**< register bits */
#define FXMAC_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define FXMAC_PHYMNTNC_PHAD_SHFT_MSK 23U     /**< Shift bits for PHYAD */
#define FXMAC_PHYMNTNC_PREG_SHFT_MSK 18U     /**< Shift bits for PHREG */
/*@}*/

/** @name transmit status register bit definitions
 * @{
 */
#define FXMAC_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define FXMAC_TXSR_URUN_MASK 0x00000040U     /**< Transmit underrun */
#define FXMAC_TXSR_TXCOMPL_MASK 0x00000020U  /**< Transmit completed OK */
#define FXMAC_TXSR_BUFEXH_MASK 0x00000010U   /**< Transmit buffs exhausted \
                                                    mid frame */
#define FXMAC_TXSR_TXGO_MASK 0x00000008U     /**< Status of go flag */
#define FXMAC_TXSR_RXOVR_MASK 0x00000004U    /**< Retry limit exceeded */
#define FXMAC_TXSR_FRAMERX_MASK 0x00000002U  /**< Collision tx frame */
#define FXMAC_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */

#define FXMAC_TXSR_ERROR_MASK ((u32)FXMAC_TXSR_HRESPNOK_MASK | \
                               (u32)FXMAC_TXSR_URUN_MASK |     \
                               (u32)FXMAC_TXSR_BUFEXH_MASK |   \
                               (u32)FXMAC_TXSR_RXOVR_MASK |    \
                               (u32)FXMAC_TXSR_FRAMERX_MASK |  \
                               (u32)FXMAC_TXSR_USEDREAD_MASK)
/*@}*/

/**
 * @name Interrupt Q1 status register bit definitions
 * @{
 */
#define FXMAC_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define FXMAC_INTQ1SR_TXERR_MASK 0x00000040U   /**< Transmit AMBA Error */

#define FXMAC_INTQ1_IXR_ALL_MASK ((u32)FXMAC_INTQ1SR_TXCOMPL_MASK | \
                                  (u32)FXMAC_INTQ1SR_TXERR_MASK)

    /*@}*/

/**
 * @name Interrupt QUEUE status register bit definitions
 * @{
 */
#define FXMAC_INTQUESR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define FXMAC_INTQUESR_TXERR_MASK 0x00000040U   /**< Transmit AMBA Error */
#define FXMAC_INTQUESR_RCOMP_MASK 0x000000001U
#define FXMAC_INTQUESR_RXUBR_MASK 0x000000004U

#define FXMAC_INTQUE_IXR_ALL_MASK ((u32)FXMAC_INTQUESR_TXCOMPL_MASK | \
                                   (u32)FXMAC_INTQUESR_TXERR_MASK)

    /*@}*/

#define FXMAC_QUEUE_REGISTER_OFFSET(base_addr, queue_id) ((u32)base_addr + (queue_id - 1) * 4)

/** @name Direction identifiers
 *
 *  These are used by several functions and callbacks that need
 *  to specify whether an operation specifies a send or receive channel.
 * @{
 */
#define FXMAC_SEND 1U /**< send direction */
#define FXMAC_RECV 2U /**< receive direction */
/*@}*/

/*GEM hs mac config register bitfields*/
#define FXMAC_GEM_HSMACSPEED_OFFSET 0
#define FXMAC_GEM_HSMACSPEED_SIZE 3

/* Transmit buffer descriptor status words offset
 * @{
 */
#define FXMAC_BD_ADDR_OFFSET 0x00000000U    /**< word 0/addr of BDs */
#define FXMAC_BD_STAT_OFFSET 0x00000004U    /**< word 1/status of BDs */
#define FXMAC_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */

/** @name MAC address register word 1 mask
 * @{
 */
#define FXMAC_GEM_SAB_MASK 0x0000FFFFU /**< Address bits[47:32] \
                                               bit[31:0] are in BOTTOM */
    /*@}*/

    /***************** Macros (Inline Functions) Definitions *********************/

#define FXMAC_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset)
#define FXMAC_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)

    void FXmacResetHw(u32 base_address);

#ifdef __cplusplus
}
#endif

#endif // !
